vhdl variable assignment in process

courses:system_design:vhdl_language_and_syntax:sequential_statements:variables

Fundamentals

• Name within process declarations
• Known only in this process
• Immediate assignment
• Keep the last value
• Signal to variable
• Variable to signal
• Types have to match

Variables can only be defined in a process and they are only accessible within this process.

Variables and signals show a fundamentally different behavior. In a process, the last signal assignment to a signal is carried out when the process execution is suspended. Value assignments to variables, however, are carried out immediately. To distinguish between a signal and a variable assignment different symbols are used: ’⇐’ indicates a signal assignment and ’:=’ indicates a variable assignment.

Variables vs. Signals

• Signal values are assigned after the process execution
• Only the last signal assignment is carried out
• M ⇐ A; is overwritten by M ⇐ C;
• The 2nd adder input is connected to C

The two processes shown in the example implement different behavior as both outputs Z and Y will be set to the result of B+C when signals are used instead of variables.

Please note that the intermediate signals have to added to the sensitivity list, as they are read during process execution.

Use of Variables

• signal to variable assignment
• execution of algorithm
• variable to signal assignments
• no access to variable values outside their process
• variables store their value until the next process call

Variables are especially suited for the implementation of algorithms. Usually, the signal values are copied into variables before the algorithm is carried out.

The result is assigned to a signal again afterwards.

Variables keep their value from one process call to the next, i.e. if a variable is read before a value has been assigned, the variable will have to show storage behavior. That means it will have to be synthesized to a latch or flip flop respectively.

Variables: Example

• Parity calculation
• Synthesis result:

In the example a further difference between signals and variables is shown. While a (scalar) signal can always be associated with a line, this is not valid for variables. In the example the for loop is executed four times. Each time the variable TMP describes a different line of the resulting hardware. The different lines are the outputs of the corresponding XOR gates.

Shared Variables (VHDL’93)

• Accessible by all processes of an architecture (shared variables)
• Can introduce non determinism

In VHDL 93, global variables are allowed.

These variables are not only visible within a process but within the entire architecture.

The problem may occur, that two processes assign a different value to a global variable at the same time. It is not clear then, which of these processes assigns the value to the variable last.

This can lead to a non deterministic behavior!

In synthesizable VHDL code global variables must not be used.

Chapters of System Design > VHDL Language and Syntax > Sequential Statements

• Sequential Statements
• IF Statement
• CASE Statement
• WAIT Statement

Chapters of System Design > VHDL Language and Syntax

• General Issues
• VHDL Structural Elements
• Process Execution
• Extended Data Types
• Subprograms
• Subprogram Declaration and Overloading
• Concurrent Statements

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The Variable: A Valuable Object in Sequential VHDL

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This article will discuss the important features of variables in VHDL.

The previous article in this series discussed that sequential statements allow us to describe a digital system in a more intuitive way. Variables are useful objects that can further facilitate the behavioral description of a circuit. This article will discuss the important features of variables. Several examples will be discussed to clarify the differences between variables and signals. Let’s first review VHDL signals.

Multiple Assignments to a Signal

VHDL uses signals to represent the circuit interconnects or wires. For example, consider the circuit in Figure 1.

The architecture of the VHDL code for this circuit is

As you can see, a signal has a clear mapping into hardware: it becomes a (group of) wire(s). Does it make sense to have multiple assignments to a signal? For example, consider the following code section:

If these two assignments are in the concurrent part of the code, then they are executed simultaneously. We can consider the equivalent hardware of the above code as shown in Figure 2.

Figure 2 suggests that multiple assignments to a signal in the concurrent part of the code is not a good idea because there can be a conflict between these assignments. For example, if A=C=0 and B=D=1, the first line would assign sig1 = (0 and 1) =0, while the second would attempt to assign sig1 = (0 or 1) = 1. That’s why, in the concurrent part of the code, VHDL doesn’t allow multiple assignments to a signal. What if these two assignments were in the sequential part of the code? A compiler may accept multiple assignments inside a process but, even in this case, only the last assignment will survive and the previous ones will be ignored. To explain this, note that a process can be thought of as a black box whose inner operation may be given by some abstract behaviour description. This description uses sequential statements. The connection between the process black box and the outside world is achieved through the signals. The process may read the value of these signals or assign a value to them. So VHDL uses signals to connect the sequential part of the code to the concurrent domain. Since a signal is connected to the concurrent domain of the code, it doesn’t make sense to assign multiple values to the same signal. That’s why, when facing multiple assignments to a signal, VHDL considers only the last assignment as the valid assignment.

Updating the Value of a Signal

The black box interpretation of a process reveals another important property of a signal assignment inside a process: When we assign a value to a signal inside a process, the new value of the signal won’t be available immediately. The value of the signal will be updated only after the conclusion of the current process run. The following example further clarifies this point. This example uses the VHDL “if” statements. Please note that we’ll see more examples of this statement in future articles; however, since it is similar to the conditional structures of other programming languages, the following code should be readily understood. You can find a brief description of this statement in a previous article.

Example: Write the VHDL code for a counter which counts from 0 to 5.

One possible VHDL description is given below:

In this example, sig1 is defined as a signal of type integer in the declarative part of the architecture. With each rising edge of clk, the value of the signal sig1 will increase by one. When sig1 reaches 6, the condition of the “if” statement in line 14 will be evaluated as true and sig1 will take the value zero. So it seems that sig1 , whose value is eventually passed to the output port out1 , will always take the values in the range 0 to 5. In other words, it seems that the “if” statement of line 14 will never let sig1 take the value 6. Let’s examine the operation of the code more closely.

Assume that a previous run of the process sets sig1 to 5. With the next rising edge of clk , the statements inside the “if” statement of line 12 will be executed. Line 13 will add one to the current value of sig1, which is 5, and assign the result to sig1 . Hence, the new value of sig1 will be 6; however, we should note that the value of the signal sig1 will be updated only after the conclusion of the current process run. As a result, in this run of the process, the condition of the “if” statement in line 14 will be evaluated as false and the corresponding “then” branch will be bypassed. Reaching the end of the process body, the value of sig1 will be updated to 6. While we intended sig1 to be in the range 0 to 5, it can take the value 6!

Similarly, at the next rising edge of clk, line 13 will assign 7 to sig1 . However, the signal value update will be postponed until we reach the end of the process body. In this run of the process, the condition of the “if” statement in line 14 returns true and, hence, line 15 will set sig1 to zero. As you see, in this run of the process, there are two assignments to the same signal. Based on the discussion of the previous section, only the last assignment will take effect, i.e. the new value of sig1 will be zero. Reaching the end of this process run, sig1 will take this new value. As you see, sig1 will take the values in the range from 0 to 6 rather than from 0 to 5! You can verify this in the following ISE simulation of the code.

Hence, when using signals inside a process, we should note that the new value of a signal will be available at the end of the current run of the process. Not paying attention to this property is a common source of mistake particularly for those who are new to VHDL.

To summarize our discussion so far, a signal models the circuit interconnections. If we assign multiple values to a signal inside a process, only the last assignment will be considered. Moreover, the assigned value will be available at the end of the process run and the updates are not immediate.

Variable: Another Useful VHDL Object

As discussed in a previous article, sequential statements allow us to have an algorithmic description of a circuit. The code of such descriptions is somehow similar to the code written by a computer programming language. In computer programming, “variables” are used to store information to be referenced and used by programs. With variables, we can more easily describe an algorithm when writing a computer program. That’s why, in addition to signals, VHDL allows us to use variables inside a process. While both signals and variables can be used to represent a value, they have several differences. A variable is not necessarily mapped into a single interconnection. Besides, we can assign several values to a variable and the new value update is immediate. In the rest of the article, we will explain these properties in more detail.

Before proceeding, note that variables can be declared only in a sequential unit such as a process (the only exception is a “shared” variable which is not discussed in this article). To get more comfortable with VHDL variables, consider the following code segment which defines variable var1 .

Similar to a signal, a variable can be of any data type (see the previous articles in this series to learn more about different data types). However, variables are local to a process. They are used to store the intermediate values and cannot be accessed outside of the process. Moreover, as shown by line 4 of the above code, the assignment to a variable uses the “:=” notation, whereas, the signal assignment uses “<=”.

Multiple Assignments to a Variable

Consider the following code. In this case, a variable, var1 , of type std_logic is defined. Then in lines 12, 13, and 14, three values are assigned to this variable.

Figure 4 shows the RTL schematic of the above code which is generated by Xilinx ISE.

It’s easy to verify that the produced schematic matches the behavior described in the process; however, this example shows that mapping variables into the hardware is somehow more complicated than that of signals. This is due to the fact that the sequential statements describe the behavior of a circuit.  As you can see, in this example, each variable assignment operation of lines 13 and 14 have created a different wire though both of these two assignments use the same variable name, i.e. var1 .

Updating the Value of a Variable

Variables are updated immediately. To examine this, we’ll modify the code of the above counter and use a variable instead of a signal. The code is given below:

Since the new value of a variable is immediately available, the output will be in the range 0 to 5. This is shown in the following ISE simulation result.

• A signal models the circuit interconnections. If we assign multiple values to a signal inside a process, only the last assignment will be considered. Moreover, the assigned value will be available at the end of the current process run and the updates are not immediate.
• A single variable can produce several circuit interconnections.
• We can assign multiple values to the same variable and the assigned new values will take effect immediately.
• Similar to a signal, a variable can be of any data type.
• Variables are local to a process. They are used to store the intermediate values and cannot be accessed outside of the process.
• The assignment to a variable uses the “:=” notation, whereas, the signal assignment uses “<=”.

To see a complete list of my articles, please visit this page .

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Variables – VHDL Example

Variables in VHDL act similarly to variables in C. Their value is valid at the exact location in the code where the variable is modified. Therefore, if a signal uses the value of the variable before the assignment , it will have the old variable value. If a signal uses the value of the variable after the assignment it will have the new variable value.

Rules of Variables:

• Variables can only be used inside processes
• Any variable that is created in one process cannot be used in another process
• Variables need to be defined after the keyword process but before the keyword begin
• Variables are assigned using the := assignment symbol
• Variables that are assigned immediately take the value of the assignment

The most important thing to understand is that variables immediately take the value of their assignment. Here’s an example that shows one useful way to use variables: storing data for temporary use . It uses a case statement and the ampersand (&) concatenation operator .

In the previous example, we concatenated the two signals so that they could be used in the case statement. The variable v_Choices was immediately available for use as soon as it was assigned. Let’s look at another example. The example below is more comprehensive and demonstrates how variables immediately take the value of their assignment. The signals r_Var_Copy1 and r_Var_Copy2 appear to be the same, but r_Var_Copy2 is never able to get to 5 before it is reset.

In order to simulate our design, we need to create a testbench . Also, variables can be a bit tricky to display in simulation. If you are using Modelsim, read more about how to see your variables in Modelsim’s waveform window .

The example above demonstrates how variables act differently from signals. The signals r_Var_Copy1 and r_Var_Copy2 appear to be the same, but r_Var_Copy2 is never able to get to 5 before it is reset.

Read more about how variables and signals are different

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Chapter 4 - Behavioral Descriptions

Section 2 - using variables.

In VHDL -93, shared variables may be declared within an architecture, block, generate statement, or package:

Using variables for registers or memory in VHDL

One question that I’ve debated many times over the years is whether it’s OK to use variables for registers in VHDL. It’s safe to say that newbies are more likely to do it than experienced VHDL designers. But is there any merit to that, or is it just a matter of preference?

In this blog post, I will try to shed some light on the issue so that you can make an informed decision about using this design practice.

First of all, let me explain what I mean by using a variable as a register.

If you read a variable in a VHDL process before you write to it, the synthesis tool will have to implement it using physical storage. That’s because its value has to be stored somewhere until the next time the process wakes up. In FPGAs, that means either registers (flip-flops) or memory (block RAM).

The code below shows an example process where my_var is not a register. The logic doesn’t rely on any previous value of the variable. We give it a default value of ‘0’ as soon as we enter the process.

If we comment out the default assignment to my_var , as shown in the example below, it becomes a register. That’s because if some_condition is false, my_signal gets whatever value my_var had the last time the process completed. You are telling the synthesis tool to remember the value of my_var over time, and the only way to do that is by using a register.

It’s perfectly legal to use variables like that in VHDL. Also, the FPGA tools won’t have any trouble implementing it most of the time. Still, it’s a design practice that’s frowned upon by many FPGA engineers. Some companies even prohibit such use of variables through their coding standards. Let’s have a look at an example and examine the pros and cons of using variables over signals.

Example using a variable to infer block RAM

In this example, I’ve created a VHDL process for inferring a dual-port RAM. The width and depth match a configuration of the Xilinx RAMB36E1 primitive, as shown on page 30 of the 7 Series FPGAs Memory Resources user guide. The code below shows the VHDL process. We store the values in the ram_v object, which is a regular variable.

When we synthesize the code in Xilinx Vivado, we see that it has indeed implemented ram_v in block RAM. Below is an excerpt from the synthesis log, showing the variable’s name mapped to a RAMB36 primitive.

Variables used for limiting the scope

A possible advantage of using a variable is that its scope is limited to within the process. Along with the variable, we can also place the type declaration of the array inside of the process. Limiting the scope of data objects is generally considered to be a good coding practice. Keeping all the constructs that “belong” to the process within it helps to refine the process as a separate design unit.

There are ways of creating limited scopes for signals as well, for example, by using the VHDL block statement . But as you can see from the example below, it adds more code lines and another indentation level to your VHDL file. I have to give a small victory to variables when it comes to encapsulation.

Line ordering matters with variables

A thing to be aware of when using variables is that the ordering of the lines matter. If we swap lines 7 and 8 in the original DUAL_PORT_RAM process, it’s broken. That’s not the case if we swap lines 12 and 13 in the code above. With signals, only which enclosure they are within matters, while with variables, the correct ordering of code lines is crucial.

Refer to my earlier blog post to understand the general difference between signals and variables: How a signal is different from a variable in VHDL

That’s one of the main objections many VHDL designers have against variables used for registers. Some engineers are accustomed to reading the code within an enclosure, like an if-statement, as parallel events. By using both variables and signals interchangeably, it becomes harder to follow the program flow. The code becomes less readable because your mind has to comprehend two constructs with different sets of rules, describing the same thing.

Of course, the arguments about readability is a subjective one. Furthermore, if you expect only signals to describe registers, you may be more inclined to overlook a variable that does the same. But if you use variables for that regularly, it may not be that big an issue for you.

Viewing variables in the ModelSim waveform

When using variables for data storage, you may want to track the value over time in the simulator. Most simulators treat variables different from signals in many ways. In ModelSim, they are not immediately accessible from the Objects window. It’s something to be aware of, but it’s a minor problem.

The video above shows how you can add a variable to the waveform in ModelSim. Bring up the Locals window by choosing View→Locals from the main menu. Select the process that contains the variable, and it will appear under Locals . Right-click the variable and add select Add Wave , just as you would with a signal.

Final thoughts

Before writing this article, I posted a question in my private Facebook group to see what other FPGA engineers had to say about using variables for storage. As I expected, most dislike using variables in this way in RTL modules. The consensus is that they are confusing to work with when they assume the same role as signals: to act as registers.

One user wrote that there’s a higher risk of creating latches with variables than signals. I’ve heard that statement before, and I tried to construct an example to demonstrate the problem, but I couldn’t. I wasn’t able to find any situations where a variable causes a latch while a signal doesn’t. Of course, that doesn’t mean that it can’t happen. But we will have to leave that statement unconfirmed at the moment.

Leave a comment if you have such an example!

Finally, a user whose first name is Ray sums up nicely what I think is the most significate argument against variables. He says:

My problem with this is that you are now relying on the synthesis tool to do “the right thing” rather than simply writing code that makes it do the right thing. I would only use variables in processes that are implementing some combinatorial logic. Then I’d register that output in a separate clocked process with its own reset.

And I have to agree on that. It’s better to be explicit in VHDL. If you want a register, it’s safest to use a signal.

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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I acknowledge the positive effect of encapsulation provided by varuables, BUT:

My coding style tends to favour short VHDL files. I,.e. I tend to prefer breaking up my design into small blocks. I seldom have files larger than 300 lines in total.

When the files are small, the benefit of encapsulation is much less.

I agree with you on that. It’s much better to break up a large architecture into a structural module with multiple submodules. The total number of files and lines increases, but so does the readability.

>> If we swap lines 7 and 8 in the original DUAL_PORT_RAM process, it’s broken.

How is it broken? It looks like write-before-read, dual port memory.

Thank you for another interesting and thought-provoking article!

Hello Andrew, that’s a good question! Let’s see what happens if we swap lines 7 and 8 in the DUAL_PORT_RAM process using variables. The listing below is from the Vivado synthesis log. It has mapped the ram_v variable to 192 RAM64M primitives, aka distributed RAM, also known as LUTRAM in Xilinx FPGAs.

Write-before-read in block RAM is only possible on the same port. By that, I mean using the same address and clock. In dual-port RAM, you can have two identical ports with separate clocks, addresses, and a write enable input. Take a look at the example code below. I have implemented one such port that has a wr_en signal that controls if we are writing to the RAM.

The code example is write-first. In the listing below, we can see that Vivado correctly mapped it to a RAMB36 block RAM primitive. Also, take note that it says WRITE_FIRST in the PORT A column, while in the Preliminary Mapping Report in the blog post, it said READ_FIRST in the same column.

I’m going to create a blog post about block RAM to clear up some misunderstandings, and also to educate myself. It’s easy to get confused with all the different configuration options that block RAM have.

>> I’m going to create a blog post about block RAM to clear up some misunderstandings, and also >> to educate myself. It’s easy to get confused with all the different configuration options that >> block RAM have.

Looking forward to that blog post Jonas!

Yes, I probably should have created that article already. It’s just that I currently have 148 future blog posts on my list. ?

Thanks for reminding me.

Vivado has some surprises. I extended your code with byte selectable write enable, which works fine for READ_FIRST

but make it WRITE_FIRST

and Vivado cannot infer the BRAM (even though this type is configurable from the IP tools). It reports

[Synth 8-2914] Unsupported RAM template

Here you have another example of using variables: The two process method from Gaisler https://www.gaisler.com/doc/vhdl2proc.pdf

This method is inline with Ray says. What do you think about it?

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In VHDL -93, a variable assignment may have a label:

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Variables in VHDL

When you declare a variable inside a process in VHDL, if you also initialise it to a certain value, i.e. a 0 or a 1, does this variable's value from previous iterations get 're-initialised' to the value you have given it?

For example every time this process is enabled by the change in the 10MHz clock, does the variable shift be initialised to 1, like the image below?

• 1 \$\begingroup\$ Maybe you should add a code snippet or so to make the question clear. \$\endgroup\$ –  Mitu Raj Commented Apr 5, 2021 at 12:05
• 1 \$\begingroup\$ @MituRaj Just added an image \$\endgroup\$ –  David777 Commented Apr 5, 2021 at 12:07
• 3 \$\begingroup\$ No. Simple answer... \$\endgroup\$ –  user16324 Commented Apr 5, 2021 at 12:49

No, it's an initialization (only for RTL simulation purpose). It will happen only once just before the simulation starts at time 0. The value of the variable, thereafter, depends on what value process drives the variable to, inside its logic (description within begin to end ), every time when the process is triggered by events of Ten_MHz_Clock .

For synthesis, these initial values are ignored by most synthesisers (I have noticed Vivado and Altera synthesisers support them on FPGA platforms), so it may not be a good coding practice for synthesisable and portable RTL, as there is a chance of synthesis-simulation mismatch at netlist level.

• 1 \$\begingroup\$ The word "simulation" needs to be highlighted here. For synthesis, initial values are ignored, so there needs to be an explicit reset mechanism. \$\endgroup\$ –  Simon Richter Commented Apr 5, 2021 at 12:37
• 1 \$\begingroup\$ yea, true...... \$\endgroup\$ –  Mitu Raj Commented Apr 5, 2021 at 12:38
• \$\begingroup\$ I always thought that the initialization values were for simulation and synthesis, that is very good to know. \$\endgroup\$ –  David777 Commented Apr 5, 2021 at 13:29
• \$\begingroup\$ So on hardware this 'shift' variable in the snippet above will be initialised as a 0? \$\endgroup\$ –  David777 Commented Apr 5, 2021 at 13:30
• 1 \$\begingroup\$ No not necessarily. Depends on the tool you use. \$\endgroup\$ –  Mitu Raj Commented Apr 5, 2021 at 13:40

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Assigning a signal to variable and a variable to a signal

I am new to VHDL and after I read through a lot of tutorials, I am now getting my feet wet. Here is a code example which troubles me. The trade_cell entity gets in a signed signal n which is assigned to a variable abs_n after getting the absolute. The result then is assigned to the signal amount for output.

Everytime I simulate this, amount is set to X. What am I missing here?

With friendly regards, RincewindWizzard

• Your code doesn't analyze, there's an extra semicolon after the last port declaration and you have extraneous sensitivity list elements that aren't declared. Fixing those two things and your code analyzes. –  user1155120 Commented May 20, 2016 at 10:10

Your problem is that this line:

is initialising the variable abs_n once at the beginning of the simulation (technically during elaboration ). At this time, the signal n will have the value 'U' and abs('U') will be 'X' , so the variable abs_n is initialised with the value 'X' and never assigned any value after that.

So, instead of:

I assume you have pared down the code to make an MCVE , which is why there are many other signals in the sensitivity list of the process trader . If not, you only need the inputs to that process in the sensitivity list (in this case just n ).

• 1 Minor typo with two := 's. ;) –  PlayDough Commented May 20, 2016 at 19:46

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