concurrent assignment statements in vhdl

• Network Sites:
• Technical Articles
• Market Insights

• Or sign in with
• iHeartRadio

Concurrent Conditional and Selected Signal Assignment in VHDL

Join our engineering community sign-in with:.

This article will review the concurrent signal assignment statements in VHDL.

This article will first review the concept of concurrency in hardware description languages. Then, it will discuss two concurrent signal assignment statements in VHDL: the selected signal assignment and the conditional signal assignment. After giving some examples, we will briefly compare these two types of signal assignment statements.

Please see my article introducing the concept of VHDL if you're not familiar with it.

Concurrent vs. Sequential Statements

To understand the difference between the concurrent statements and the sequential ones, let’s consider a simple combinational circuit as shown in Figure 1.

Figure 1. A combinational circuit.

If we consider the operation of the three logic gates of this figure, we observe that each gate processes its current input(s) in an independent manner from other gates. These physical components are operating simultaneously. The moment they are powered, they will “concurrently” fulfill their functionality. Note that while, in practice, the AND gate has a delay to produce a valid output, this does not mean that the OR gate will stop its functionality and wait until the output of the AND gate is produced. The OR gate will function all the time; however, its output will not be valid until its inputs have settled.

Now, let’s examine the VHDL description of Figure 1. This is shown below:

The main part that we are here interested in is the definition of the three gates:

Each of these lines describes a physical component in Figure 1. For example, the second line, which describes the OR gate, takes sig1 and c as inputs and produces the OR of these two values. We saw that the physical components of Figure 1 operate concurrently. Hence, it is reasonable to expect that the VHDL description of these gates should be evaluated in a concurrent manner. In other words, the above three lines of the code are executed at the same time and there is no significance to the order of these statements. As a result, we can rewrite the architecture section of the above code as below:

Since these statements are evaluated at the same time, we call them concurrent statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other. For example, consider the following MATLAB code:

This code produces out1=1 and out2=1 . However, if we change the order of the statements to the following, the program will stop working because we are trying to use sig1 before it is generated.

While the VHDL code describing Figure 1 was executed concurrently, the above MATLAB code is evaluated sequentially (i.e., one line after the other). VHDL supports both the concurrent statements and the sequential ones. It's clear that the concurrent VHDL statements will allow us to easily describe a circuit such as the one in Figure 1 above. In a future article, we'll see that the sequential VHDL statements allow us to have a safer description of sequential circuits. Furthermore, using the sequential VHDL, we can easily describe a digital circuit in a behavioral manner. This capability can significantly facilitate digital hardware design.

The following figure illustrates the difference between concurrent and sequential statements.

Figure 2. The difference between concurrent and sequential statements. Image courtesy of VHDL Made Easy .

Now let's take a look at two concurrent signal assignment statements in VHDL: “the selected signal assignment statement” and “the conditional signal assignment statement”.

Selected Signal Assignment or the “With/Select” Statement

Consider an n -to-one multiplexer as shown in Figure 3. This block should choose one out of its n inputs and transfer the value of this input to the output terminal, i.e., output_signal .

Figure 3. A multiplexer selects one of its n inputs based on the value of the control_expression.

The selected signal assignment allows us to implement the functionality of a multiplexer. For example, the VHDL code describing the multiplexer of Figure 3 will be

Here, the value of the control_expression will be compared with the n possible options, i.e., option_1 , option_2 , …, option_n . When a match is found, the value corresponding to that particular option will be assigned to the output signal, i.e., output_signal . For example, if control_expression is the same as option_2 , then value_2 will be assigned to the output_signal .

Note that the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options. The following example clarifies these points.

Example 1 : Use the "with/select" statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code for this multiplexer is given below:

Note that since the std_logic data type can take values other than “0” and “1” , the last line of the “with/select” statement needs to use the keyword “ others ” to take all the possible values of sel into account.

The following figure shows the simulation of this code using the Xilinx ISE simulator. (In case you’re not familiar with ISE, see this tutorial .) As shown in this figure, from 0 nanosecond (ns) until 300 ns the select input, sel , is 00, and, hence, out1 follows the input a . Similarly, you can verify the intended operation for the rest of the simulation interval.

Figure 4. The ISE simulation for the multiplexer of Example 1.

Example 2 : Use the “with/select” statement to describe a 4-to-2 priority encoder with the truth table shown below.

The following VHDL code can be used to describe the above truth table:

The ISE simulation is shown in Figure 5.

Figure 5. The ISE simulation for the priority encoder of Example 2.

Conditional signal assignment or the “when/else” statement.

The “when/else” statement is another way to describe the concurrent signal assignments similar to those in Examples 1 and 2. Since the syntax of this type of signal assignment is quite descriptive, let’s first see the VHDL code of a one-bit 4-to-1 multiplexer using the “when/else” statement and then discuss some details.

Example 3 : Use the when/else statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code will be

In this case, the expressions after “when” are evaluated successively until a true expression is found. The assignment corresponding to this true expression will be performed. If none of these expressions are true, the last assignment will be executed. In general, the syntax of the “when/else” statement will be:

We should emphasize that the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones. Considering this, we can obtain the conceptual diagram of this assignment as shown in Figure 6. This figure illustrates a conditional signal assignment with three “when” clauses.

Figure 6. The conceptual implementation of a “when/else” statement with three “when” clauses.

Let’s review the main features of the selected signal assignment and the conditional signal assignment.

“With/Select” vs. “When/Else” Assignment

As mentioned above, the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of options. While the “with/select” assignment has a common controlling expression, a “when/else” assignment can operate on expressions with different arguments. For example, consider the following lines of code:

In this case, the expressions are evaluating two different signals, i.e., reset1 and clk .

For the “when/else” assignment, we may or may not include all the possible values of the expressions to be evaluated. For example, the multiplexer of Example 3 covers all the possible values of sel ; however, the above code does not. The above code implies that out1 should retain its previous value when none of the expressions are true. This causes the inference of a latch in the synthesized circuit.

Another important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The priority network of Figure 6 involves a cascade of several logic gates. However, the “with/select” assignment avoids this chain structure and has a balanced structure. As a result, in theory, the “with/select” statement may have better performance in terms of the delay and area (see RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability , Xilinx HDL Coding Hints , and Guide to HDL Coding Styles for Synthesis ).

In practice, we generally don’t see this difference because many synthesis software packages, such as the Xilinx XST, try not to infer a priority encoded logic. Though we can use the PRIORITY_EXTRACT constraint of XST to force priority encoder inference, Xilinx strongly suggests that we use this constraint on a signal-by-signal basis; otherwise, the constraint may guide us towards sub-optimal results. For more details see page 79 of the XST user guide .

• Concurrent statements are executed at the same time and there is no significance to the order of these statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other.
• The selected signal assignment or the "with/select" assignment allows us to implement the functionality of a multiplexer.
• The options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options.
• For the "when/else" statement, the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones.
• One important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The "when/else" statement has a priority network; however, the “with/select” assignment avoids this chain structure and has a balanced structure.

To see a complete list of my articles, please visit  this page .

  Featured image used courtesy of Parallella .

Related Content

• Safety in Sensing: Sensor Technology in Smart Cities
• Thermocouple Signal Conditioners and Signal Conditioning Near the Cold Junction
• Reducing Distortion in Tape Recordings with Hysteresis in SPICE
• Test & Measurement in Quantum Computing
• Open RAN – Network Performance in the Lab and in the Field
• Looking for Good Waves: The Importance of Signal Integrity in High-Speed PCB Design

Learn More About:

• programmable logic

Great content. The link to the ISE guide requires password. Can we get that posted again? Thanks!

You May Also Like

Get 15% off our Comprehensive Selection of Connectors and More

In Partnership with Future Electronics

ST Releases Flagship Low-Power MCUs and New Process Technology

by Jake Hertz

onsemi’s Offline SMPS System Solution Guide

by Future Electronics

AMD Builds New Ryzen Processors on Zen 5 Architecture for Advanced AI

by Aaron Carman

How to Design Reliable Next-Gen Automotive Control Electronics

by James Colby, Littelfuse

Welcome Back

Don't have an AAC account? Create one now .

Forgot your password? Click here .

How to create a concurrent statement in VHDL

A concurrent statement in VHDL is a signal assignment within the architecture, but outside of a normal process construct. The concurrent statement is also referred to as a concurrent assignment or concurrent process.

When you create a concurrent statement, you are actually creating a process with certain, clearly defined characteristics. Concurrent statements are always equivalent to a process using a sensitivity list, where all the signals to the right of the signal assignment operator are on the sensitivity list.

These shorthand notation processes are useful when you want to create simple logic which results in the assignment of a single signal. Instead of typing out a full process construct with sensitivity lists and all of that, you can simply assign to the target signal directly in the architecture.

This blog post is part of the Basic VHDL Tutorials series.

When used correctly, the intention of the code will still be pretty clear. No need to create a process for every single bit you want to flip.

In this video, we learn how to create a concurrent statement:

The final code we created in this tutorial:

The waveform window in ModelSim after we pressed run, and zoomed in on the timeline:

Need the Questa/ModelSim project files?

Let me send you a Zip with everything you need to get started in 30 seconds

By submitting, you consent to receive marketing emails from VHDLwhiz (unsubscribe anytime).

We can see from the waveform that Mul1 , Mul2 , and Mul3 behave exactly the same. This is because the concurrent statement and the two processes we created are equivalent.

A concurrent statement works just like a process. All signals to the right of the <= are automatically added to the sensitivity list. This means that the signal to the left of the <= will be updated whenever one of the signals that are evaluated change.

There are many ways to multiply numbers in VHDL. In this exercise we multiplied the Uns signal by 4, using bit shifting. All our signals are of unsigned type, meaning that they are interpreted by numbers. Appending a 0 to the right of a binary number is the same as multiplying it by 2.

Get free access to the Basic VHDL Course

Download the course material and get started.

You will receive a Zip with exercises for the 23 video lessons as VHDL files where you fill in the blanks, code answers, and a link to the course.

• A concurrent statement is a signal assignment directly in the architecture region
• Concurrent statements are equivalent to a process with all evaluated signals on the sensitivity list

Go to the next tutorial »

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

Similar Posts

How to use Wait On and Wait Until in VHDL

In the previous tutorial we learned the main differences between signals and variables. We learned that signals have a broader scope than variables, which are only accessible within one process. So how can we use signals for communication between several processes? We have already learned to use wait; to wait infinitely, and wait for to…

How to create a signal vector in VHDL: std_logic_vector

The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it. While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections…

How to stop simulation in a VHDL testbench

How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run. The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving…

How to use a Case-When statement in VHDL

The Case-When statement will cause the program to take one out of multiple different paths, depending on the value of a signal, variable, or expression. It’s a more elegant alternative to an If-Then-Elsif-Else statement with multiple Elsif’s. Other programming languages have similar constructs, using keywords such as a switch, case, or select. Among other things,…

RC servo controller using PWM from an FPGA pin

Radio-controlled (RC) model servos are tiny actuators typically used in hobbyist model planes, cars, and boats. They allow the operator to control the vehicle via a radio link remotely. Because RC models have been around for a long time, the de-facto standard interface is pulse-width modulation (PWM), rather than a digital scheme. Fortunately, it’s easy…

How to use a function in VHDL

Functions are subprograms in VHDL which can be used for implementing frequently used algorithms. A function takes zero or more input values, and it always returns a value. In addition to the return value, what sets a function apart from a procedure, is that it cannot contain Wait-statements. This means that functions always consume zero…

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Notify me of replies to my comment via email

Concurrent Statements

Cite this chapter.

• Stanley Mazor 2 &
• Patricia Langstraat 2  

263 Accesses

This chapter discusses VHDL concurrent statements. It contains the following sections:

The Process

Concurrent Signal Assignment

Conditional Signal Assignment

Selective Signal Assignment

Concurrent Procedure Call

BLOCK Statement

A hardware description language documents systems that perform parallel operations. During simulation, components in these systems are “run” at the same simulated time, as explained earlier in Chapter 5. Concurrent statements are used to express this kind of parallel behavior. Concurrent descriptions can be structural (using components — see Chapter 7) or behavioral. The key concurrent statement is the process that is described in detail in Chapter 3.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save.

• Get 10 units per month
• Download Article/Chapter or eBook
• 1 Unit = 1 Article or 1 Chapter
• Cancel anytime
• Available as PDF
• Read on any device
• Instant download
• Own it forever
• Compact, lightweight edition
• Dispatched in 3 to 5 business days
• Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Unable to display preview.  Download preview PDF.

Author information

Authors and affiliations.

Synopsys, Inc., USA

Stanley Mazor & Patricia Langstraat

You can also search for this author in PubMed   Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 1992 Springer Science+Business Media Dordrecht

About this chapter

Mazor, S., Langstraat, P. (1992). Concurrent Statements. In: A Guide to VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2114-0_6

Download citation

DOI : https://doi.org/10.1007/978-1-4757-2114-0_6

Publisher Name : Springer, Boston, MA

Print ISBN : 978-1-4757-2116-4

Online ISBN : 978-1-4757-2114-0

eBook Packages : Springer Book Archive

Share this chapter

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

• Publish with us

Policies and ethics

• Find a journal
• Track your research

VHDL Concurrent Conditional Assignment

The Conditional Signal Assignment statement is concurrent because it is assigned in the concurrent section of the architecture. It is possible to implement the same code in a sequential version, as we will see next.

The conditional signal assignment statement is a process that assigns values to a signal.

It is a concurrent statement; this means that you must use it only in concurrent code sections.

The statement that performs the same operation in a sequential environment is the “ if ” statement.

The syntax for a conditional signal assignment statement is:

This is a simple example of a two-way mux as reported here:

The output “ a ” is equal to “ b ” when the selector “ c ” is “1” else is equal to “ d ”

Concurrent Conditional Signal Assignment Example 1

This example extends the previous one. This is a 4-way mux, implemented as concurrent code.

The architecture declarative section is empty. As you can notice, we don’t care about how the mux is implemented.

In this moment we don’t’ talk about logic gate, and or nand ect, we are describing the behavior of circuit using a high level description.

A graphical representation can be this one.

It is up to the synthesizer to implement the best architecture on the selected technology in terms of logic gates. In fact if you are using FPGA the synthesizer will use LUT to map the VHDL functions, if you are implementing an ASIC the synthesized logic will depend on differ technology and will be implemented using, for instance, NAND, OR, NOR gate, depending on the technology.

Running the RTL compiler on Altera Quartus II , this is the output of the RTL viewer, if we try to layout this mux4 .

As clear, the RTL translation is implemented in terms of AND gate and 2-way mux. The output “ e ” is generated by cascading 3 two-way mux.

This is the output of the Altera MAP viewer selecting Cyclone IV FPGA technology. Our mux4 is implemented using LOGIC_COMB_CELL Look Up Table present in the Cyclone IV FPGA . This example should clarify the meaning of “technology dependent”.

Concurrent Conditional Signal Assignment Example 2

This example is the same 4-way mux as the previous one, in which we used a different syntax to implement the selector. In this case, we have introduced the statement “with select”.

In the architecture declarative section, we declared a signal “ sel ” of type integer used to address the mux. The signal “ sel ” is coded as binary to integer.

The statement “ with select ” allows compacting the syntax of the mux code. Note the introduction of the “ other ” keyword. It is necessary because the mux assignment cover only 3 of the 2^32 possible integer values. If we try to layout the code, it is interesting to see how RTL viewer interprets the VHDL code:

This case is different from the previous one. We can notice that the VHDL relative to the signal sel is decoded in order to implement mux selection and that the output mux is implemented as 4-way mux. So the RTL view of the RTL code is totally different from the previous one.

The FPGA used in this example is the same as the previous example, in fact the output of Altera MAP viewer have the same implementation of the previous RTL code as clear if we make a comparison between the two implementations.

These two examples should clarify the meaning of behavioral. We have seen two different implementations of a simple mux mapped on the same hardware :

implementation of different RTL code can generate the same hardware logic.

Of course, gaining the sensibility to write good VHDL/RTL code is only a matter of time and experience . If you will follow the course, you will find good advices in order to gain all the shortcuts useful reduce this amount of time.

  Previous  – Next

Concurrent Signal Assignments :

Useful resources.

• Mini Projects
• MATLAB Projectss
• VLSI Projects
• Arduino Projects

vhdl_reference_93:concurrent_signal_assignment

Concurrent signal assignment ,... <= ..."

Concurrent_signal_assignment_statement.

• architecture_statement_part
• block_statement_part

Further definitions

Conditional_signal_assignment.

target <= options conditional_waveforms ;

selected_signal_assignment

with expression select target <= options selected_waveforms ;

Additional information

With a conditional signal assignment there is always an equivalent process statement; in general, this is valid for all concurrent assignments.

The equivalent process statement of a concurrent signal assignment statement including the keyword POSTPONED is a postponed process.

If the conditional signal assignment has the form

the signal assignment in the corresponding process statement has the form

If the (conditional) waveform is a simple waveform the signal assignment in the corresponding process statement has the form

The process statement of the wave_transform of a waveform of the form

has the form

null is here a null statement, not a null transaction!

The waveforms` characteristics and the conditions contained in the signal assignment have to be formulated appropriately so that the IF-statement in the corresponding process statement is a permitted statement.

With a selecting signal assignment there is always an equivalent process statement. If the selecting signal assignment has the form

For wave_transform look at the previous topic on conditional signal assignment.

The characteristics of the selected expression, of the waveforms and the criteria of selection contained in the signal assignment have to be formulated appropriately so that the CASE statement in the corresponding process statement is a permitted statement.

If the option GUARDED is contained in the signal assignment it is a so-called controlled assignment. If the target is also controlled the statement part of the corresponding process statement looks as follows:

If the target is not controlled the statement part of the corresponding process statement looks as follows:

It is also possible that neither signal assignment nor target is controlled. If this is the case the statement part of the corresponding process statement looks as follows:

It is not permitted to handle a signal assignment as being not controlled while handling the corresponding target as being controlled!

The value of b is assigned to the signal a after 5ns. In the first case the inertial delay model and in the second case the transport delay model is used.

The controlled signal assignment is only carried out if the corresponding condition in the block declaration is fulfilled.

If sel=0 then a is assigned the value 1 after 5ns; if sel=1 then a is assigned the value 0 after 3ns and the value 1 after 5ns; otherwise a is given the value X after 2 ns.

In this value assignment to the signal sig the value of of muxval is taken into consideration.

If muxval=0 then sig is assigned the value 001 etc. For this assignment the delay model TRANSPORT is used irrespective of the value of muxval .

S is only driven if the driver value is different the current value of S ; otherwise nothing happens.

Stack Exchange Network

Stack Exchange network consists of 183 Q&A communities including Stack Overflow , the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Q&A for work

Connect and share knowledge within a single location that is structured and easy to search.

VHDL Concurrent statement comparison

I am learning VHDL and came across this example of 2 functionally equivalent ways of implementing the same thing. But I am having trouble understanding how they are functionally equivalent.

My confusion is in the 3 concurrent statement picture. Since they are all executed at the same time that means that F3 gets set to (A1 or A2). But since A1 and A2 are getting set at the same time that F3 is getting set, doesn't that mean A1 and A2 do not actually have values yet when F3 tries to get assigned to (A1 or A2)?

• 1 \$\begingroup\$ This may help. BASIC CONCEPTS SIMULATION MODEL DELTA TIME - CONCURRENCY . The first point is telling - "VHDL was designed as a simulation language, so to understand the language we must examine the behavior of a VHDL simulator". \$\endgroup\$ –  user8352 Commented Nov 19, 2020 at 7:31
• \$\begingroup\$ thank you @user8352 your answer lead me to figuring it out. I answered the question in a way that makes sense to me and posted it on this thread. I think me showing the screenshots how I did will make it clear for other beginners like me. \$\endgroup\$ –  Eric33 Commented Nov 20, 2020 at 17:15

4 Answers 4

There's a lot of technical details to simulation and instantiation. But I'd like to avoid the algebraic approaches and just focus on the visual aspects for a moment. It may help. (You've avoided variables, but I may decide to address them for a moment below.)

It's probably better if you think of a signal as the same thing as a named wire . So when you write the following within a begin..end block:

All it is doing is the following:

simulate this circuit – Schematic created using CircuitLab

Note that the order of the statements don't matter. They could be arranged in any permutation you wanted. The same schematic results from those three statements, regardless of order.

Your signal names are just wires with names. That's all. The only difference between the above and what results from:

simulate this circuit

In other words, two named wires are no longer named. That's all that happens. Since naming is a matter of convenience for humans, not for circuits, it makes no difference in the combinatorial result.

Now, there is a difference with VHDL variables. If you are familiar with C, it's perhaps better to see a variable as if it were the equivalent of a C #define and not as a physical wire in a schematic.

For example, if A1 and A2 were variables instead of signals, then:

Would produce the same logic as in the second schematic above, except perhaps the following might be a better way of seeing it:

No wires are really named A1 or A2 . Instead, the expressions for A1 and A2 were, in effect, inserted into the wire-assignment for F3 . (You could still label those wires, mentally. But it's better to imagine they aren't named at all, but instead just used to replace the symbols in the final line where the wire F3 is assigned.)

There are some subtle and not-so-subtle results from this difference.

In VHDL gate-level logic, you can add an after clause to a signal assignment. But you cannot do that with a variable. That's because a variable isn't a wire representing the output of some logic. It really is more like the C language's #define.

So you can write:

And this will affect simulation (but not instantiation.)

But, if A1 and A2 were variables, you cannot write:

Variables cannot have delays like that. The above would be an error. This is because the variables replace their mnemonics found in wire assignments (the <= lines.) Variables are not wires. (Besides, the very idea of subexpressions with after clauses together with a final after clause on that wire assignment line would be quite confusing!)

Where all this actually gets interesting is in sequential logic (RTL) where you are indicating sensitivity to a std_logic signal's clock edge. Then the differences in variables and signal wires becomes far more interesting.

Assuming A1 and A2 are variables:

You get this (where only F3 depends on the rising edge of CLK (std_logic type), as A1 and A2 are more like "macros" representing some logic but not actual wires ):

A variable represents a block of logic and not a wire. It is meaningless to imagine that the block is sensitive to an edge of CLK . Only signal wires can be. When a wire is placed within an if..end that depends upon a rising or falling edge of some other std_logic wire, this infers an FF. As a variable isn't a wire, an FF cannot be inferred for a variable.

That is very much different from the following case where A1 and A2 are signals/wires (which do depend upon the rising edge of CLK ):

When you instead get:

Hopefully, that helps a little.

VHDL shouldn't be treated like a programming language. VHDL is a hardware description language. Whatever codes written in concurrent section have nothing to do with "time", and the order of codes doesn't matter. That means it's equivalent to a circuit operating at "all times", i.e. independent of time.

• 1 \$\begingroup\$ That all depends on your definition of programming language. You will find that in functional programming languages like Haskell, the statement order doesn't describe temporal sequence either; a VHDL concurrent region behaves similar to that. \$\endgroup\$ –  user16324 Commented Nov 18, 2020 at 20:25
• 1 \$\begingroup\$ @BrianDrummond, but that's a tiny minority compared to the vast majority of software which is written in procedural programming languages. So there's no confusion caused by the term 'programming language'. \$\endgroup\$ –  TonyM Commented Nov 18, 2020 at 22:01

This is not a sequential program, but a description of connections in a circuit, so F3 is connected to the output of an OR gate that has its inputs connected to A1 and A2 .

The difference between the two approaches is whether you give names to intermediates. A similar thing can happen in sequential languages, for example in C the statements

are equivalent.

The book is a bit confusing here -- the equivalence is not a result of concurrency.

Due to the concurrency, you can also swap the VHDL statements and still get the same result, while that doesn't work in C.

I spent some time researching what @user8352 linked me to, delta cycles. I'm sure if you are experienced with VHDL then you can answer my question easily.

I took screenshots of how I was able to see everything step by step. The code, the simulation and a table explaining the current time, current signal values and time until the next event are shown in each screenshot.

I understand what they mean now, the result is the same, just the number of delta cycles are different. That is what I had imagined (some sort of timing difference) but could not explain why.

Your Answer

Sign up or log in, post as a guest.

Required, but never shown

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy .

Not the answer you're looking for? Browse other questions tagged vhdl or ask your own question .

• The Overflow Blog
• Mobile Observability: monitoring performance through cracked screens, old...
• Featured on Meta
• Announcing a change to the data-dump process
• Bringing clarity to status tag usage on meta sites

Hot Network Questions

• How can I Align an existing Object to the 3D Viewport's XY Plane?
• Is it possible to travel to USA with legal cannabis?
• A classic problem about matrix
• What happens to entropy during compression?
• Reference request: regularity of non-divergence form elliptic operators with Neumann boundary conditions
• Best way to explain the thinking steps from x² = 9 to x=±3
• Journal keeps messing with my proof
• Can taut membranes and strings that are clamped at both ends propagate non-standing waves?
• Bash script that takes multiple path arguments and checks if files can be successfully created there
• Why is the !? annotation so rare?
• What is the difference between "Hubiera" and "Habría"?
• When a star becomes a black hole do the neutrons that are squeezed together release binding energy and if so does this energy escape from the hole?
• Does it pay to put effort in fixing this problem or better reinstall Ubuntu 24.04 from scratch?
• Why are orthonitrate ions not found in nature?
• If you have two probabilities, how do you describe how much more likely one is than the other?
• Why is simpler prose more popular these days?
• What does ציר"ו stand for?
• Should you refactor when there are no tests?
• If Starliner returns safely on autopilot, can this still prove that it's safe? Could it be launched back up to the ISS again to complete its mission?
• Who owns code contributed to a license-free repository?
• How many ways can you make change?
• How make this table? And which package more helpful for these tables
• How to setup a home lab with a custom domain name?
• Does the TLS_ECDHE_ECDSA_WITH_AES_256_CCM ciphersuite support the sha 384 hash function?

• Stack Overflow for Teams Where developers & technologists share private knowledge with coworkers
• Advertising & Talent Reach devs & technologists worldwide about your product, service or employer brand
• OverflowAI GenAI features for Teams
• OverflowAPI Train & fine-tune LLMs
• Labs The future of collective knowledge sharing
• About the company Visit the blog

Collectives™ on Stack Overflow

Find centralized, trusted content and collaborate around the technologies you use most.

Q&A for work

Connect and share knowledge within a single location that is structured and easy to search.

Get early access and see previews of new features.

multiple assignment of concurrent statement

The following code gives me an error, which I can't figure out myself. The error is because there are multiple assignments of output d0

• register-transfer-level

A for-generate creates concurrent logic that is replicated multiple times. You have specified 10 assignments to d0 . Effective use of generate statements typically requires the use of array types as the targets of assignments to organize the different concurrent elements. Optionally, you may be able to use resolved types to manage multiple drivers of a single signal but that isn't typically useful outside of simulation.

It looks like you're trying to describe a mux using a one-hot selection. This can be accomplished without a generate statement. Think about the logic involved in creating a mux and describe the relevant boolean operations in parallel using arrays.

Your Answer

Reminder: Answers generated by artificial intelligence tools are not allowed on Stack Overflow. Learn more

Sign up or log in

Post as a guest.

Required, but never shown

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy .

Not the answer you're looking for? Browse other questions tagged vhdl digital register-transfer-level vlsi or ask your own question .

• The Overflow Blog
• Mobile Observability: monitoring performance through cracked screens, old...
• Featured on Meta
• Announcing a change to the data-dump process
• Bringing clarity to status tag usage on meta sites
• What does a new user need in a homepage experience on Stack Overflow?
• Feedback requested: How do you use tag hover descriptions for curating and do...
• Staging Ground Reviewer Motivation

Hot Network Questions

• Does it pay to put effort in fixing this problem or better reinstall Ubuntu 24.04 from scratch?
• Functor composition rule necessary?
• How can I Align an existing Object to the 3D Viewport's XY Plane?
• Reference to formal approach to homotopy analysis method
• World Building Knowledgebase - How to write good Military World Building
• I have two identical LaTeX files, with different file names. Only one yields "undefined references." Why is this happening?
• Can an international student email a professor at a foreign university for an internship opportunity?
• Journal keeps messing with my proof
• Is it valid to replace the limit of a function inside the indifnite integration when computing limits?
• Did Gandalf know he was a Maia?
• decode the pipe
• Lore reasons for being faithless
• How to disavow backlinks from the Bing group of websites?
• Why does Jenny hug Cindy at the end of "Commando" (1985)?
• What story starts off with the character waking up in a battlefield with wolves and vultures and snow?
• How make this table? And which package more helpful for these tables
• What does "if you ever get up this way" mean?
• What should be the affiliation of PhD student who submitted thesis but yet to defend, in a conference talk slides?
• Why are orthonitrate ions not found in nature?
• Identifications in differential geometry
• Is it a date format of YYMMDD, MMDDYY, and/or DDMMYY?
• What are the common traits of US backed regime change?
• Expensive constructors. Should they exist? Should they be replaced?
• Whats the safest way to store a password in database?