research paper topics on vlsi technology

Conference proceedings
© 2021

VLSI-SoC: Design Trends

28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

Andrea Calimera ORCID: https://orcid.org/0000-0001-5881-3811 0 ,
Pierre-Emmanuel Gaillardon ORCID: https://orcid.org/0000-0003-3634-3999 1 ,
Kunal Korgaonkar ORCID: https://orcid.org/0000-0002-9078-2944 2 ,
Shahar Kvatinsky ORCID: https://orcid.org/0000-0001-7277-7271 3 ,
Ricardo Reis ORCID: https://orcid.org/0000-0001-5781-5858 4

Politecnico di Torino, Turin, Italy

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University of Utah, Salt Lake City, USA

Technion – israel institute of technology, haifa, israel, universidade federal do rio grande do sul, porto alegre, brazil.

Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT, volume 621)

Conference series link(s): VLSI-SoC: IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip

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Conference proceedings info: VLSI-SoC 2020.

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Table of contents (16 papers)

Front matter, low-power high-speed adcs for adc-based wireline receivers in 22 nm fdsoi.

David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot et al.

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring

Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta et al.

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform

Alessandro Veronesi, Davide Bertozzi, Milos Krstic

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays

Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek

Learning Based Timing Closure on Relative Timed Design

Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication

Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

From Informal Specifications to an ABV Framework for Industrial Firmware Verification

Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli

Modular Functional Testing: Targeting the Small Embedded Memories in GPUs

Josie Esteban Rodriguez Condia, Matteo Sonza Reorda

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

Jonas Gava, Ricardo Reis, Luciano Ost

SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption

Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs

Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Arnaud Poittevin, Chhandak Mukherjee, Ian O’Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng et al.

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics

Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, Arijit Raychowdhury

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory

Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky

Back Matter

Other volumes.

The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs.

*The conference was held virtually.

artificial intelligence
communication systems
computer hardware
computer-aided design
distributed computer systems
distributed systems
embedded systems
field programmable gate array
integrated circuits
microprocessor chips
network protocols
parallel processing systems
signal processing
telecommunication systems
vlsi circuits

Andrea Calimera

Pierre-Emmanuel Gaillardon

Kunal Korgaonkar, Shahar Kvatinsky

Ricardo Reis

Book Title : VLSI-SoC: Design Trends

Book Subtitle : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers

Editors : Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis

Series Title : IFIP Advances in Information and Communication Technology

DOI : https://doi.org/10.1007/978-3-030-81641-4

Publisher : Springer Cham

eBook Packages : Computer Science , Computer Science (R0)

Hardcover ISBN : 978-3-030-81640-7 Published: 15 July 2021

Softcover ISBN : 978-3-030-81643-8 Published: 15 July 2022

eBook ISBN : 978-3-030-81641-4 Published: 14 July 2021

Series ISSN : 1868-4238

Series E-ISSN : 1868-422X

Edition Number : 1

Number of Pages : XVIII, 364

Number of Illustrations : 70 b/w illustrations, 139 illustrations in colour

Topics : Computer Systems Organization and Communication Networks , Control Structures and Microprogramming , Input/Output and Data Communications , Information Systems Applications (incl. Internet)

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research paper topics on vlsi technology

Dr. Brajesh Kumar Kaushik

Professor Indian Institute of Technology, Roorkee Editor in Chief Journal of VLSI Design Tools and Technology

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Journal of VLSI Design Tools & Technology

Domino Logic Circuit

Fft processor, round robin arbiter, high-level synthesis for vlsi systems.

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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits

Design of Decoder Using Domino Logic Circuit for VLSI

Design and Simulation of Forging Die Towards Improving Life of Closed Die

About the Journal

Journal of VLSI Design Tools and Technology (jovdtt) : 2249-474X(e) is a peer-reviewed hybrid open-access journal launched in 2015 focused on the rapid publication of fundamental research papers on all areas of VLSI Design Tools & Technology. View Full Focus and Scope…

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Latest Research topics in vlsi design

Latest research topics in vlsi design.

If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

As the research fields we are talking about are providing base to the developing world and providing it with reliable technologies which are being used in real time, the work of researcher becomes more wide starting with an idea to the realization of the idea in the real world in form of application or product.

To make a reliable and working model the idea of the VLSI design project ( i.e speech processing application, biomedical monitoring system etc) needs to be implemented and re-implemented, re-tested and improvised. The there are many development cycles and techniques available which eases up the implementation like:

Behavioral simulation
Software based model
Hardware Implementation (ASIC)
Programmable hardware (FPGA)
Co-simulation

Behavioral simulation is used at initial phase and it is not appropriate for testing the real time behavior of the system in actual environment as it is more close to systems behavior in ideal environment.

We can simulate the actual environment by using different software models (more like software models of channels used to test communication systems) but its capabilities are also limited to human capability to model the environmental conditions in mathematical equations and models.

All of us are familiar with ASIC, their high performance and hardwired implementation. These are good for final implementation but not for intermediate stages of implementation and testing. Nothing is better than ASIC for real time testing of analog VLSI circuits. But for digital circuits and DSP applications we have a better option of FPGA (Field Programmable Gate Array).

The hardware co-simulation is a good idea to test and monitor systems in real time. To get more details about PhD thesis in VLSI you can do online research or contact us.

latest Low power research topics in vlsi design

The Research Support Centre provides expert advice and support across the whole Engineering and Technical research lifecycle, from discovery through exploitation of technical and translational research. The centre has two primary functions:

i) to facilitate the delivery of the Engineering Sciences research strategy and to build partnerships andii) to bring together all the technical research management and support services for Students.

To achieve these goals the centre is made up of two inter-relating components. The Academic Research Support Centre consists of the Research Coordination Office, Platform Technologies team and a Translational Research Office. The Technical Research Support Centre is made up of the Joint Research Office.

The Research Support Centre encompasses a wide range of expertise and facilities. By coordinating these resources, we can provide researchers with a package of support that is integrated, high quality and streamlined – and clearly accountable.

Once a researcher has a proposal for high quality research that will benefit, they can access all the help and resources they need through one gateway. This includes support with the approval process and funding applications and help setting up technical trials.

VLSI PHD Projects

Our research interests cover low power processor architectures, low power circuit design techniques, analog and mixed signal circuit design, rapid prototyping of digital systems, reconfigurable processors, Digital arithmetic, advanced processor architectures, vlsi implementation of signal and image processing algorithms, testing verification, memory design, Embedded vlsi and asynchronous circuits.

Organization engaged with embedded commodity development and serving various business solutions such as

Embedded System Product Development,
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Web development.

Description for “Ph.d guidance with project assitance” Ph.d/ M.Phil PROJECT ASSISTANCE We look forward to welcoming you to one of our “Research and Development Division” for all Ph.D., Research scholars. We will arrange you the following details for completing your Ph.d Degree

Any University Admission- We provides a step-to-step guide to completing the application form, and will help make the process as straight forward as possible.
Guide Arrangement
Survey Paper Preparation
Problem Identification –Problem Identification of Existing System.
Implementation in all domains
Mobile Ad hoc Networks
Wireless Networks
Image Processing
Grid Computing
Distributed Computing
Natural Language Processing
Cloud Computing
Soft Computing
Data Mining
Wireless Senor Networks

Delivering effective support on your Ph. D work:

Companies represents a simple and practical advice on the problems of getting started, getting organized with the working on Ph.D projects.

We make you understand the practicalities of surviving the ordeal. We just make you divide the huge task into less challenging pieces. The training includes a suggested structure and a guide to what should go in each section.

We afford complete support with real-time exposure in your Ph.D works in the field of VLSI. Our Mission drives us in the way of delivering applications as well as products with complete integrity, innovative & interesting ideas with 100% accuracy.

Assistance in ALL Stages of your PhD Research in VLSI from Topic Selection to Thesis Submission.
Creating 100% confident in submitting your thesis work.
Our experienced professionals support you in your research works.
Providing complete solutions for the Research Scholars in many advanced domains.

Technologies used in VLSI:

Modelsim 6.5b Simulator
Xilinx ISE 10.1 System generator

III. Quartus 11.1

Tanner v7 EDA tool

iii. W-Edit

Microwind & DSCH v2

VII. P-spice

VIII. LT-spice

. Spartan IIIe

Hardware Description Language

. Verilog HDL

CORE AREA OF GUIDANCE:

Digital signal processing Vlsi
Image processing Vlsi

III. Wireless Vlsi

Communication Vlsi
Testing Vlsi
Digital cmos Vlsi

VII. low power Vlsi

VIII. Core Vlsi

Memory Designs

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Screenshots

III. Simulation Report

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Block Diagrams
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VII. Software Development Standards & Procedure – E-Book

Learning Exposure:

VIII. Programming classes

Practical training
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Publishing Support:

XII. Conference Support

XIII. Journal Support

XIV. Guide Arrangements

Vlsi based projects like image processing projects, low power projects, matlab with vlsi projects , cryptography projects, OFDM projects, SDR projects, communication projects, zigbee projects, digital signal processing projects, and also protocol interfacing projects like uart ,i2c,spi projects.

Signal and Image processing projects can be simulated by using Modelsim 6.5b and synthesized by Xilinx 10.1 using Spartan IIIe fpga and by Quartus 11.1using altera de2 fpga. In image processing projects, the input image or video can be converted to coefficients using Matlab. Low power projects can be designed using Tanner, Microwind and spice tools.

We spotlights on imparting an overall exposure to the concept and design methodologies of all major aspects of vlsi engineering relevant to industry needs and ground-breaking thoughts with 100% pure accuracy.

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Back propagation neural network based power estimation method for CMOS VLSI circuits

Low power vlsi design techniques: a review.

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Technologies for creating radiation-resistant VLSI

The technology of radiation-resistant CMOS VLSI is based on industrial IC technology. The design uses feedback circuits and guard rings to compensate for single effects of cosmic particles (SEE). In most critical cases, these influences in digital circuits lead to single faults (SEU), which temporarily disrupt the state of memory cells, to latching (SEL), and in the long term to a catastrophic change of state. Various space programs confirm great prospects for their use in future space structures. The article discusses the effects of using radiation-resistant CMOS technology, technology based on a silicon-on-sapphire structure, CMOS technology on an insulating substrate taking into account typical characteristics, SIMOX-SOI technology, which consists in separation by implantation of oxygen ions. In new designs of circuits, more advanced algorithms should be implemented for the future.

Machine Learning Based Power Estimation for CMOS VLSI Circuits

Abstract The authors have requested that this preprint be withdrawn due to a need to make corrections.

Abstract Nowdays, machine learning (ML) algorithms are receiving massive attention in most of the engineering application since it has capability in complex systems modelling using historical data. Estimation of power for CMOS VLSI circuit using various circuit attributes is proposed using passive machine learning based technique. The proposed method uses supervised learning method which provides a fast and accurate estimation of power without affecting the accuracy of the system. Power estimation using random forest algorithm is relatively new. Accurate estimation of power of CMOS VLSI circuits is estimated by using random forest model which is optimized and tuned by using multi-objective NSGA-II algorithm. It is inferred from the experimental results testing error varies from 1.4 percent to 6.8 percent and in terms of and Mean Square Error is 1.46e-06 in random forest method when compared to BPNN. Statistical estimation like coefficient of determination (𝑅) and Root Mean Square Error (RMSE) are done and it is proven that random Forest is best choice for power estimation of CMOS VLSI circuits with high coefficient of determination of 0.99938. and low RMSE of 0.000116.

Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Revisiting the Utility of Transmission Gate and Passtransistor Logic Styles in CMOS VLSI Design

Peculiarities of appearance and registration of the latchup in cmos vlsi under uniform pulsed laser irradiation, export citation format, share document.

Georgia Tech Faculty to Present Timely Topics at VLSI Symposium on Technology and Circuits

May 19, 2022 — atlanta, ga.

In June, some of the world’s top technologists in the VLSI (Very Large-Scale Integration) industry will convene in Honolulu for the 2022 IEEE Symposium on VLSI Technology and Circuits , one of the premier symposiums for microelectronics and semiconductor research. Now in its 42 nd year, the VLSI Symposium offers attendees the opportunity to share and exchange ideas on the most relevant subjects in their fields and address current and future directions in the development of VLSI technology.

Given the continuing global semiconductor shortage, the theme of this year’s conference is “Technology and Circuits for the Critical Infrastructure of the Future.” Seven papers submitted by Georgia Tech faculty have been accepted and will be presented during the conference. Paper topics include Ferroelectric Memories, Resistive Memories, Embedded DRAM, and Power Converter based on GaN/Si. The contributing professors include Asif Khan, Arijit Raychowdhury, Shimeng Yu, and Suman Datta from Georgia Tech’s Institute of Electronics and Nanotechnology (IEN) and the School of Electrical and Computer Engineering (ECE).

In addition to presenting their papers, Datta and Yu are also organizing short courses on Monolithic and Heterogenous Integration and Advances in Application-Specific Computing Systems and Technologies. Muhannad Bakir will present on “2.5D and 3D Polylithic Integration Technologies” as part of the course on Monolithic and Heterogenous Integration.

“The VLSI Symposium is one of the most selective and prestigious venues to publish the latest advances in semiconductor technologies and circuits, and it has always had a strong industry presence,” said Raychowdhury, who also serves as the Steve W. Chaddick School Chair in ECE. “Our participation through multiple papers and invited talks is a clear testament of the depth and breadth of our research program. Congratulations to all of the students and faculty members who are making us proud through their impactful research.”

About the contributors:

Arijit Raychowdhury is the Steve W. Chaddick School Chair and Professor at ECE. His research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. He holds more than 25 U.S. and international patents and has published over 80 articles in journals and refereed conferences. He holds a Ph.D. in electrical and computer engineering from Purdue University and a B.E. in electrical and telecommunication engineering from Jadavpur University in India.

Muhannad Bakir is the Dan Fielder Professor in ECE. His research interests include heterogeneous microsystem design and integration, including 2.5D and 3D ICs and packaging, advanced cooling and power delivery for emerging system architectures; electrical and photonic interconnect technologies; biosensor technologies and their integration with CMOS; and nanofabrication technologies. Bakir is an editor of IEEE Transactions on Electron Devices and an associate editor of IEEE Transactions on Components , Packaging and Manufacturing Technology.

Suman Datta will join the Georgia Tech faculty this fall as Joseph M. Pettit Chair in ECE and a Georgia Research Alliance (GRA) Eminent Scholar. He will also have a joint appointment with the School of Materials Science and Engineering (MSE). His research involves high-performance, heterogenous computing, brain-inspired computing, and collective state computing using advanced CMOS (complementary metal–oxide–semiconductor) and beyond-CMOS devices. He also focuses on the development of semiconductor technologies for other types of computing, including intermittent computing, cryogenic computing, and harsh environment computing.

Asif Khan is an assistant professor in ECE with a courtesy appointment in MSE. His research focuses on microelectronic devices, specifically on ferroelectric devices that address the challenges faced by the semiconductor industry due to the end of transistor miniaturization. His research group at Georgia Tech focuses on all aspects of ferroelectricity ranging from materials physics, growth, and electron microscopy to micro- and nano-fabrication of electronic devices, all the way to ferroelectric circuits and systems for artificial intelligence, machine learning, and data-centric applications.

Shimeng Yu is an associate professor in ECE. He has both a master’s and Ph.D. in electrical engineering from Stanford University and a B.S. in microelectronics from Peking University. His research interests lie in nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security.

The IEEE Symposium on VLSI Technology and Circuits is a five-day hybrid event known as the microelectronics industry’s premiere international conference integrating technology, circuits, and systems with a range and scope unlike any other conference. In addition to the technical presentations, the Symposium program will feature a demonstration session, evening panel discussions, joint focus sessions, short courses, workshops, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposia theme. To learn more visit http://www.vlsisymposium.org .

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Second round of seed grants awarded to MIT scholars studying the impact and applications of generative AI

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Last summer, MIT President Sally Kornbluth and Provost Cynthia Barnhart issued a call for papers to “articulate effective roadmaps, policy recommendations, and calls for action across the broad domain of generative AI.” The response to the call far exceeded expectations with 75 proposals submitted. Of those, 27 proposals were selected for seed funding .

In light of this enthusiastic response, Kornbluth and Barnhart announced a second call for proposals this fall.

“The groundswell of interest and the caliber of the ideas overall made clear that a second round was in order,” they said in their email to MIT’s research community this fall. This second call for proposals resulted in 53 submissions.

Following the second call, the faculty committee from the first round considered the proposals and selected 16 proposals to receive exploratory funding. Co-authored by interdisciplinary teams of faculty and researchers affiliated with all five of the Institute’s schools and the MIT Schwarzman College of Computing, the proposals offer insights and perspectives on the potential impact and applications of generative AI across a broad range of topics and disciplines.

Each selected research group will receive between $50,000 and $70,000 to create 10-page impact papers. Those papers will be shared widely via a publication venue managed and hosted by the MIT Press under the auspices of the MIT Open Publishing Services program.

As with the first round of papers, Thomas Tull, a member of the MIT School of Engineering Dean’s Advisory Council and a former innovation scholar at the School of Engineering, contributed funding to support the effort.

The selected papers are:

“A Road-map for End-to-end Privacy and Verifiability in Generative AI,” led by Alex Pentland, Srini Devadas, Lalana Kagal, and Vinod Vaikuntanathan;
“A Virtuous Cycle: Generative AI and Discovery in the Physical Sciences,” led by Philip Harris and Phiala Shanahan;
“Artificial Cambrian Intelligence: Generating New Forms of Visual Intelligence,” led by Ramesh Raskar and Tomaso A. Poggio;
“Artificial Fictions and the Value of AI-Generated Art,” led by Justin Khoo;
“GenAI for Improving Human-to-human Interactions with a Focus on Negotiations,” led by Lawrence Susskind and Samuel Dinnar;
“Generative AI as a New Applications Platform and Ecosystem,” led by Michael Cusumano;
“Generative AI for Cities: A Civic Engagement Playbook,” led by Sarah Williams, Sara Beery, and Eden Medina;
“Generative AI for Textile Engineering: Advanced Materials from Heritage Lace Craft,” led by Svetlana V. Boriskina;
“Generative AI Impact for Biomedical Innovation and Drug Discovery,” led by Manolis Kellis, Brad Pentelute, and Marinka Zitnik;
“Impact of Generative AI on the Creative Economy,” led by Ashia Wilson and Dylan Hadfield-Menell;
“Redefining Virtuosity: The Role of Generative AI in Live Music Performances,” led by Joseph A. Paradiso and Eran Egozy;
“Reflection-based Learning with Generative AI,” led by Stefanie Mueller;
“Robust and Reliable Systems for Generative AI,” led by Shafi Goldwasser, Yael Kalai, and Vinod Vaikuntanathan;
“Supporting the Aging Population with Generative AI,” led by Pattie Maes;
“The Science of Language in the Era of Generative AI,” led by Danny Fox, Yoon Kim, and Roger Levy; and
“Visual Artists, Technological Shock, and Generative AI,” led by Caroline Jones and Huma Gupta.

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MIT scholars awarded seed grants to probe the social implications of generative AI

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